Manycore performance analysis using timed configuration graphs

Bengtsson, JerkerHögskolan i Halmstad,Centrum för forskning om inbyggda system (CERES) (författare)

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The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.

NATURVETENSKAP Data- och informationsvetenskap Datorteknik hsv//swe
NATURAL SCIENCES Computer and Information Sciences Computer Engineering hsv//eng
graphs
microcomputers
parallel architectures
parallel programming
program compilers
software performance evaluation
task analysis
Computer engineering
Datorteknik

Svensson, BertilHögskolan i Halmstad,Centrum för forskning om inbyggda system (CERES)(Swepub:hh)bertil (författare)
Högskolan i HalmstadCentrum för forskning om inbyggda system (CERES) (creator_code:org_t)

Ingår i:International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09Piscataway, N.J. : IEEE Press, s. 108-1179781424445028

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