Asynchronous BFT for low power networks on chip

• Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

BFT

GALS

Low power

NoC

Publikations- och innehållstyp

ref (ämneskategori)

kon (ämneskategori)