Concept and design of exhaustive-parallel search algorithm for Network-on-Chip

• This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 88 mesh architecture and its performance is evaluated.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Circuit-switch (CS)

Exhaustive Parallel Search (EPS)

Guaranteed Throughput (GT)

Network-on-Chip (NoC)

Guaranteed throughputs

High performance switches

Mesh architecture

Minimal path

Network on chip

Parallel search

Search Algorithms

Learning algorithms

Microprocessor chips

Servers

VLSI circuits

Programmable logic controllers

Publikations- och innehållstyp

ref (ämneskategori)

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