Sökning: WFRF:(Mohammed Mohammed A.)
> (2005-2009) >
High throughput arc...
High throughput architecture for CLICHÉ network on chip
-
Abd El Ghany, M. A. (författare)
-
El-Moursy, M. A. (författare)
-
- Ismail, Mohammed (författare)
- KTH,Elektroniksystem,(RaMSiS Group)
-
(creator_code:org_t)
- 2009
- 2009
- Engelska.
-
Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2009. - 9781424452200 ; , s. 155-158
- Relaterad länk:
-
https://urn.kb.se/re...
-
visa fler...
-
https://doi.org/10.1...
-
visa färre...
Abstract
Ämnesord
Stäng
- High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- CLICHÉ
- Latency
- NoC
- Throughput
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
Hitta via bibliotek
Till lärosätets databas