HiWA : A hierarchical Wireless Network-on-Chip architecture

• Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in WNoCs. Thus, in this paper, we introduce a hierarchical WNoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are almost handled by single-hop wireless links. On top of that, we have also defined performance evaluation parameters. Simulation results show that the proposed architecture reduces average packet latency 16% and power consumption 14% in comparison with its conventional counterparts.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)

Nyckelord

Architecture

Latency

Network-on-Chip

Power Consumption

System-on-Chip

Wireless Network-on-Chip

Application specific integrated circuits

Computer architecture

Distributed computer systems

Electric power utilization

Microprocessor chips

Network architecture

Servers

VLSI circuits

Wireless interconnects

Wireless networks

Wireless telecommunication systems

Average packet latencies

Efficient communications

Evaluation parameters

High power consumption

Proposed architectures

Wireless communication links

Wireless transceiver

Publikations- och innehållstyp

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