Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits

• This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

inverter

NAND

nonoverlapping clock generation circuit (CGC)

NOR

power-supply noise (PSN)

substrate noise

timing jitter

phase noise

pll jitter

delay

oscillators

impact

model

Publikations- och innehållstyp

ref (ämneskategori)

art (ämneskategori)