Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model

• A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)

Nyckelord

AMBA bus

Complementary graph

Fault model

SoC

State graph

Buses

Graphic methods

Programmable logic controllers

System-on-chip

Extensive simulations

Graph-based techniques

High-level fault models

On chip communication

State graphs

Testing

Publikations- och innehållstyp

ref (ämneskategori)

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