SwePub
Sök i LIBRIS databas

  Utökad sökning

L773:0038 1101 OR L773:1879 2405
 

Sökning: L773:0038 1101 OR L773:1879 2405 > (2015-2019) > Process optimizatio...

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

Qin, Changliang (författare)
Wang, Guilei (författare)
Hong, Peizhen (författare)
visa fler...
Liu, Jinbiao (författare)
Yin, Huaxiang (författare)
Yin, Haizhou (författare)
Ma, Xiaolong (författare)
Cui, Hushan (författare)
Lu, Yihong (författare)
Meng, Lingkuan (författare)
Xiang, Jinjuan (författare)
Zhong, Huicai (författare)
Zhu, Huilong (författare)
Xu, Qiuxia (författare)
Li, Junfeng (författare)
Yan, Jian (författare)
Zhao, Chao (författare)
Radamson, Henry H. (författare)
KTH,Integrerade komponenter och kretsar
visa färre...
 (creator_code:org_t)
Elsevier, 2016
2016
Engelska.
Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 123, s. 38-43
  • Tidskriftsartikel (refereegranskat)
Abstract Ämnesord
Stäng  
  • In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Mosfet
SiGe
Source/drain recess
Epitaxy
Source/drain extension implant
22 nm node

Publikations- och innehållstyp

ref (ämneskategori)
art (ämneskategori)

Hitta via bibliotek

Till lärosätets databas

Kungliga biblioteket hanterar dina personuppgifter i enlighet med EU:s dataskyddsförordning (2018), GDPR. Läs mer om hur det funkar här.
Så här hanterar KB dina uppgifter vid användning av denna tjänst.

 
pil uppåt Stäng

Kopiera och spara länken för att återkomma till aktuell vy