Hierarchical Design of a Low Power Standing Wave Oscillator Based Clock Distribution Network

• This paper introduces a hierarchical clock interconnection network with two-level bufferless standing wave resonant clock distribution to minimize the clock power consumption in a synchronous system. The first level is a serpentine network which consists of many coupled standing wave oscillators to distribute clock signals in the whole chip area. The second level is a group of fishbone architectures connected to the standing wave oscillators to route clock signals in the local areas. A clock synthesis flow for the fishbone architecture is also introduced to enable design automation. This fishbone architecture is studied through a pipelined floating-point fused multiply-add module under 28nm standard CMOS process. Simulation results show that, this architecture can reduce more than 30% clock power consumption compared with a traditional buffered clock network.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Standing wave oscillator

Clock distribution network

Clock synthesis

Clock power

Publikations- och innehållstyp

ref (ämneskategori)

kon (ämneskategori)