Scalability of Network-on-Chip Communication Architecture for 3-D Meshes

QC 20110301
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

TEKNIK OCH TEKNOLOGIER Elektroteknik och elektronik Annan elektroteknik och elektronik hsv//swe
ENGINEERING AND TECHNOLOGY Electrical Engineering, Electronic Engineering, Information Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering hsv//eng
3D networks
Communication architectures
Communication schemes
Communication topologies
Cycle accurate
Design constraints
Design guidelines
Global interconnect delay
Integrated electronics
Network on chip
Technology solutions
Through silicon vias
Traffic pattern
Biological materials
Electric network topology
Interconnection networks
Microprocessor chips
Network performance
Routers
Scalability
Systems engineering
Three dimensional
Electronics
Elektronik

Grange, Matt (author)
Pamunuwa, Dinesh (author)
Lu, ZhonghaiKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1wqy6h0 (author)
Jantsch, AxelKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u18wycaf (author)
Weerasekera, Roshan (author)
Tenhunen, HannuKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1wjjaxp (author)
KTHElektronik- och datorsystem, ECS (creator_code:org_t)

In:2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIPNEW YORK : IEEE, s. 114-1239781424441426

By the author/editor: Weldezion, Awet ...; Grange, Matt; Pamunuwa, Dinesh; Lu, Zhonghai; Jantsch, Axel; Weerasekera, Ros ...; show more...; Tenhunen, Hannu; show less...

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ENGINEERING AND TECHNOLOGY: ENGINEERING AND ...; and Electrical Engin ...; and Other Electrical ...

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