Scalability of Network-on-Chip Communication Architecture for 3-D Meshes

• Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

3D networks

Communication architectures

Communication schemes

Communication topologies

Cycle accurate

Design constraints

Design guidelines

Global interconnect delay

Integrated electronics

Network on chip

Technology solutions

Through silicon vias

Traffic pattern

Biological materials

Electric network topology

Interconnection networks

Microprocessor chips

Network performance

Routers

Scalability

Systems engineering

Three dimensional

Electronics

Elektronik

Publication and Content Type

ref (subject category)

kon (subject category)