Dependable I2C Communication with FPGA

• This work introduces the I2C bus availability problem for Cube Satellites and robotics applications. It suggests the use of FPGAs as an alternative to microcontroller systems as they are capable of recovering from bus faults via partial reconfiguration without mission interruption, and triple wire redundancy is feasible because more pins are available. The proposed topology makes use of 3 AXI IIC IP core instances, a TMR voter, and a comparator along with a watchdog timer to detect faults and recover from them. The bus successfully recovered from fault injections instantly with IIC resets and after 17 ms via partial reconfiguration, occupying 5% of the LUTs, 1% of the LUTRAMs, 3% of Flip Flops and IO, consuming 1.684W with a total of 2.43% essential bits.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Inbäddad systemteknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Embedded Systems (hsv//eng)

Nyckelord

I2c

Fault tolerance

Reliability

Data bus

Partial reconfiguration

FPGA

Cubesat

Robotics

High availability

Dependable computing

Publikations- och innehållstyp

ref (ämneskategori)

kon (ämneskategori)