Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh

• The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Inbäddad systemteknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Embedded Systems (hsv//eng)

Keyword

cycle-accurate RTL simulator;horizontal network link;multiclock 3-dimensional network-on-chip mesh architecture;on-chip interconnect;physical mapping;switches;system-level impact;through silicon vias;vertical network link;integrated circuit interconnections;network analysis;network-on-chip

Publication and Content Type

ref (subject category)

kon (subject category)