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Multi-FPGA Implemen...
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Chen, XiaowenKTH,Elektroniksystem
(author)
Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism
- Article/chapterEnglish2010
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LIBRIS-ID:oai:DiVA.org:kth-63631
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https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-63631URI
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https://doi.org/10.1109/NORCHIP.2010.5669430DOI
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Language:English
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Summary in:English
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Subject category:ref swepub-contenttype
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Subject category:kon swepub-publicationtype
Notes
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Key: Nostrum. QC 20120209
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In this paper, we propose a fast barrier synchronization mechanism, targetingNetwork-on-Chip based manycore architectures. Its salient feature is that, once thebarrier condition is reached, the "barrier release" acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization of barrierreleasing. Then, we construct a multi-FPGA platform using Xilinx® Virtex 5 as FPGA chipsand implement a NoC based many-core architecture on it. FPGA utilization and simulation results show that our mechanism demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing.
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Chen, Shuming
(author)
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Lu, ZhonghaiKTH,Elektroniksystem(Swepub:kth)u1wqy6h0
(author)
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Jantsch, AxelKTH,Elektroniksystem(Swepub:kth)u18wycaf
(author)
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Xu, Bangjian
(author)
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Luo, Heng
(author)
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KTHElektroniksystem
(creator_code:org_t)
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In:Proceedings of the IEEE Norchip Conference9781424489732
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