Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism

Key: Nostrum. QC 20120209
In this paper, we propose a fast barrier synchronization mechanism, targetingNetwork-on-Chip based manycore architectures. Its salient feature is that, once thebarrier condition is reached, the "barrier release" acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization of barrierreleasing. Then, we construct a multi-FPGA platform using Xilinx® Virtex 5 as FPGA chipsand implement a NoC based many-core architecture on it. FPGA utilization and simulation results show that our mechanism demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing.

TEKNIK OCH TEKNOLOGIER Elektroteknik och elektronik hsv//swe
ENGINEERING AND TECHNOLOGY Electrical Engineering, Electronic Engineering, Information Engineering hsv//eng
Barrier synchronization
Completion time
FPGA chips
Many-core architecture
Multi-FPGA
Network on chip
Processor nodes
Salient features
Simulation result
Source nodes
Unicast

By the author/editor: Chen, Xiaowen; Chen, Shuming; Lu, Zhonghai; Jantsch, Axel; Xu, Bangjian; Luo, Heng

About the subject

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