A performance and energy exploration of dictionary code compression architectures

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We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.

Brorsson, Mats,1962-KTH,Programvaru- och datorsystem, SCS,Kista Multicore Center(Swepub:kth)u1dkd5v9 (författare)
Öberg, JohnnyKTH,Elektroniksystem(Swepub:kth)u1t0l5al (författare)
KTHProgramvaru- och datorsystem, SCS (creator_code:org_t)

Ingår i:2011 International Green Computing Conference and Workshops (IGCC): IEEE conference proceedings, s. 1-89781457712227

Av författaren/redakt...: Collin, Mikael; Brorsson, Mats, ...; Öberg, Johnny

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