Wafer-Level Via-First 3D Integration with Hybrid-Bonding of Cu/BCB Redistribution Layers

• Three-dimensional (3D) integration with through-die viasoffer improved electrical performance compared to edgeconnectedwire bonds in stacked-die assemblies for wirelessapplications. Monolithic wafer-level 3D integration offersthe potential for a high density of micron-sized through-dievias necessary for highest performance memory stacks,microprocessors with large L2 caches and ASICs with largeembedded memories. In addition, such wafer-leveltechnologies offer the potential of lowest cost in largemanufacturing volume of any heterogeneous integrationplatform, incorporating the inherent low cost of monolithicIC interconnectivity. After a brief summary of current wafer-level 3D integrationplatforms, a recently introduced platform that offers theprocess integration advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength andenvironmental robustness of dielectric adhesive bondingusing benzocyclobutene (BCB) is discussed. Criticalprocessing challenges of the new platform include BCBpartial curing compatible with damascene patterning, postdamascene-patterning cleaning and surface activation,bonding process parameters, and wafer-level planarizationrequirements. The inherent incorporation of a redistributionlayer into the bonding layer process further reduces theprocess flow and is compatible with wafer-level packaging(WLP) technologies.

Nyckelord

3D

high-density interconnect

wafer-level

redistribution layers

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