A 6.2 GFLOPS Floating Point Multiply-Accumulator with Conditional Normalization

• A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic with delayed addition is described. A combination of algorithmic, logic, and circuit techniques enables multiply-accumulate operations at speeds exceeding 3 GHz with single-cycle throughput. The optimizations allow removal of the costly normalization step from the critical accumulate loop. This logic is conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading-zero anticipator (LZA) and overflow prediction logic applicable to carry-save format is presented. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFlops of performance while dissipating 1.2 W at 3.1 GHz, 1.3-V supply

Nyckelord

CMOS logic circuits

adders

floating point arithmetic

multiplying circuits

1.2 W

1.3 V

90 nm

CMOS digital integrated circuits

algorithmic technique

carry-save arithmetic

circuit technique

conditional normalization

delayed addition

floating-point multiply-accumulator

leading-zero anticipator

logic technique

overflow prediction logic

TECHNOLOGY

TEKNIKVETENSKAP

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