Simulation and evaluation of an architecture based on asynchronous processes

• Much research today is devoted to finding new and improved computer architectures in which parallel computations can be performed, the goal being an exploitation of the natural parallelism inherent in many problem descriptions. This thesis describes a register level simulator for a family of architectures based on asynchronous processes. An important aspect of this class of architectures is its modularity. Within the architecture, we hope to avoid the problem of dynamically binding every operation as in dataflow machines. A silicon compiler can use the modularity of descriptions to perform various optimizations on instances of the architecture. The simulator is written in a language called Occam, in which parallel execution at the statement level can be expressed. A short description of the language is given and some of the issues of designing, testing and maintaining concurrent programs are discussed. The added complexity of parallelism especially makes the debugging phase very difficult.

Ämnesord

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)

Publikations- och innehållstyp

vet (ämneskategori)

lic (ämneskategori)