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Low-Latency Paralle...
Low-Latency Parallel Hermitian Positive-Definite Matrix Inversion for Massive MIMO
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- Bertilsson, Erik, 1990- (författare)
- Linköpings universitet,Datorteknik,Tekniska fakulteten
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- Ingemarsson, Carl, 1983- (författare)
- Linköpings universitet,Datorteknik,Tekniska fakulteten
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- Gustafsson, Oscar, 1973- (författare)
- Linköpings universitet,Datorteknik,Tekniska fakulteten
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(creator_code:org_t)
- Institute of Electrical and Electronics Engineers (IEEE), 2021
- 2021
- Engelska.
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Ingår i: 2021 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2021). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781665401449 - 9781665401456 ; , s. 23-28
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- In this work, the effect of latency for three different positive definite matrix inversion algorithms when implemented on parallel and pipelined processing elements is considered. The work is motivated by the fact that in a massive MIMO system, matrix inversion needs to be performed between estimating the channels and producing the transmitted downlink signal, which means that the latency of the matrix inversion has a significant impact on the system performance. It is shown that, despite the algorithms having different complexity, all three algorithms can have the lowest latency for different number of processing elements and pipeline levels. Especially, in systems with many processing elements, the algorithm with the highest complexity has the lowest latency.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Signalbehandling (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Signal Processing (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Telekommunikation (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Telecommunications (hsv//eng)
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