id:"swepub:oai:DiVA.org:liu-46237"
Search: id:"swepub:oai:DiVA.org:liu-46237" > Efficient test solu...
- 1 of 1
- Previous record
- Next record
- To hitlist
- Larsson, ErikLinköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system (author)
Efficient test solutions for core-based designs
- Article/chapterEnglish2004
Publisher, publication year, extent ...
- 2004
- printrdacarrier
Numbers
- LIBRIS-ID:oai:DiVA.org:liu-46237
- https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-46237URI
- https://doi.org/10.1109/TCAD.2004.826560DOI
Supplementary language notes
- Language:English
- Summary in:English
Part of subdatabase
- SwePubSwePub
Classification
Notes
- A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.
Subject headings and genre
- scan-chain partitioning
- system-on-chip (SOC) testing
- test access mechanism design
- test data transportation
- test scheduling
- test solutions
- TECHNOLOGY
- TEKNIKVETENSKAP
Added entries (persons, corporate bodies, meetings, titles ...)
- Arvidsson, KlasLinköpings universitet,Tekniska högskolan,Institutionen för datavetenskap(Swepub:liu)klaar36 (author)
- Fujiwara, H (author)
- Peng, ZeboLinköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system(Swepub:liu)zebpe83 (author)
- Linköpings universitetTekniska högskolan (creator_code:org_t)
Related titles
- In:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems23:5, s. 758-7750278-00701937-4151
Internet link
Find in a library
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Search for host publication in LIBRIS)
To the university's database
- 1 of 1
- Previous record
- Next record
- To hitlist
Find more in SwePub
- By the author/editor
- Larsson, Erik
- Arvidsson, Klas
- Fujiwara, H
- Peng, Zebo
- Articles in the publication
- IEEE Transaction ...
- By the university
- Linköping University
Search outside SwePub
- Extend your search to:
- Google Book Search
- Google Scholar
Kungliga biblioteket hanterar dina personuppgifter i enlighet med EU:s dataskyddsförordning (2018), GDPR. Läs mer om hur det funkar här.
Så här hanterar KB dina uppgifter vid användning av denna tjänst.
- Copyright © LIBRIS - National Library Systems
- LIBRIS.kb.se
