Two-tone PLL for on-chip IP3 test

Ahmad, Shakeel,1977-Linköpings universitet,Elektroniska komponenter,Tekniska högskolan (author)

This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

Azizi, KavehLinköpings universitet,Elektroniska komponenter,Tekniska högskolan (author)
Esmaeil Zadeh, ImanLinköpings universitet,Elektroniska komponenter,Tekniska högskolan (author)
Dabrowski, Jerzy,1952-Linköpings universitet,Elektroniska komponenter,Tekniska högskolan(Swepub:liu)jerda40 (author)
Linköpings universitetElektroniska komponenter (creator_code:org_t)

In:Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10): IEEE, s. 3549-35529781424453085

By the author/editor: Ahmad, Shakeel, ...; Azizi, Kaveh; Esmaeil Zadeh, I ...; Dabrowski, Jerzy ...

Kungliga biblioteket hanterar dina personuppgifter i enlighet med EU:s dataskyddsförordning (2018), GDPR. Läs mer om hur det funkar här.
Så här hanterar KB dina uppgifter vid användning av denna tjänst.