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Using DSP block pre...
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs
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- Ingemarsson, Carl, 1983- (författare)
- Linköpings universitet,Elektroniksystem,Tekniska högskolan
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- Källström, Petter, 1980- (författare)
- Linköpings universitet,Elektroniksystem,Tekniska högskolan
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- Gustafsson, Oscar, 1973- (författare)
- Linköpings universitet,Elektroniksystem,Tekniska högskolan
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(creator_code:org_t)
- Piscataway, NJ, USA : IEEE Communications Society, 2012
- 2012
- Engelska.
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Ingår i: 22nd International Conference on Field Programmable Logic and Applications (FPL). - Piscataway, NJ, USA : IEEE Communications Society. - 9781467322560 - 9781467322553 ; , s. 71-74
- Relaterad länk:
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https://urn.kb.se/re...
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visa fler...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
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