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Simulation-driven development of a novel SiC embedded power module design concept

Zhang, Yafan (author)
KTH,RISE,Acreo,Elkraftteknik,RISE Acreo AB, Sweden
Neumaier, Klaus (author)
ON Semiconductor Gmhb, Germany; Fairchild Semiconductor Gmhb, Germany
Zschieschang, Olaf (author)
ON Semiconductor Gmhb, Germany; Fairchild Semiconductor Gmhb, Germany
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Weis, Gerald (author)
AT & S Austria Technologie & Systemtechnik, Austria
Schmid, Gerhard (author)
AT & S Austria Technologie & Systemtechnik, Austria
Bakowski, Mietek (author)
RISE,Acreo
Nee, Hans-Peter (author)
KTH,Elkraftteknik,KTH Royal Institute of Technology, Sweden
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 (creator_code:org_t)
Institute of Electrical and Electronics Engineers (IEEE), 2017
2017
English.
In: 2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509043446
  • Conference paper (peer-reviewed)
Abstract Subject headings
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  • Silicon carbide embedded power modules enable a compact and cost competitive packaging solution for high-switching frequency and high-temperature operation applications. Power module packaging technologies span several engineering domains. At the early design stage, simulation-driven development is necessary to shorten the design period and reduce the design cost. This paper presents a novel design concept of a three-phase embedded power module (1200 V, 20 A, 55 mm × 36 mm × 0.808 mm) including silicon carbide metal-oxide-semiconductor field-effect transistor and antiparallel diode dies. Based on the E/CAD design data different layer built-up designs have been tested against thermal, mechanical, and electrical behavior. The obtained simulation data then have been evaluated against a commercial available power module (Motion Smart Power Module SMP33) which utilizes over mold direct bonded copper substrates with soldered semiconductor dies and bond wire contacts. Compared to the conventional module, the loop conductive interconnection parasitic inductance and resistance of the design concept (Vdc+ to Vdc-) reduces approximately by 88 % and 72 %, respectively. The average junction to case thermal resistance has been improved by approximately more than 10 % even though the total package size reduces by approximately 88 %. Furthermore, the contours of deformation and stresses have been investigated for the design concept in the thermomechanical simulation.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

Carbide dies
Chip scale packages
Field effect transistors
High temperature applications
High temperature operations
Metals
Microelectronics
Microsystems
MOS devices
MOSFET devices
Oxide semiconductors
Semiconducting silicon
Silicon carbide
Substrates
Wide band gap semiconductors
Anti-parallel diodes
Deformation and stress
Direct bonded coppers
Early design stages
Electrical behaviors
High switching frequencies
Parasitic inductances
Thermomechanical simulation
Electric power systems

Publication and Content Type

ref (subject category)
kon (subject category)

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