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Ultra Low Energy De...
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
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- Sherazi, Syed Muhammad Yasser (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Rodrigues, Joachim (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Akgun, OmerCan (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Sjöland, Henrik (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Nilsson, Peter (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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(creator_code:org_t)
- Elsevier BV, 2013
- 2013
- Engelska.
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Ingår i: Microprocessors and Microsystems. - : Elsevier BV. - 0141-9331. ; 37:4-5, s. 494-504
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. Simulation results show that the unfolded by 2 and 4 architectures are the most energy efficient for throughput requirements between 250 ksamples/s, and 2Msamples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164 fJ and 205 fJ, with single supply voltage of 260mV.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- Energy dissipation
- Ultra Low Power
- Decimation filters
- Half band filters
- 65 nm
- Sub-threshold
- CMOS
- Unfolding
- Wireless devices
- Implantable devices.
Publikations- och innehållstyp
- art (ämneskategori)
- ref (ämneskategori)
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