Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation

• echniques are evaluated for implementing error- correction codes (ECC) in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub- VT implementation is predicted to offer 29× gain in power consumption for a (3,6) LDPC decoder of length N = 512 operating at a throughput of 200Mbps, compared to standard digital implementation of the same design.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Error correction codes

sub-threshold

ultra-low voltage

analog decoders

biomedical implants

Publikations- och innehållstyp

art (ämneskategori)

ref (ämneskategori)