A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

• This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Signalbehandling (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Signal Processing (hsv//eng)

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kon (ämneskategori)

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