Area and power efficient trellis computational blocks in 0.13μm CMOS

• Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

rate 1/2 convolutional codes

complementary property

trellis-based decoding architectures

reduced complexity

trellis computational blocks

cell area

CMOS process

branch metric unit

add-compare-select unit

0.13 micron

power consumption

silicon implementation

Publication and Content Type

kon (subject category)

ref (subject category)