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A low latency and a...
A low latency and area efficient FFT processor for massive MIMO systems
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- Mahdavi, Mojtaba (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Integrated Electronic Systems,Lund University Research Groups
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- Edfors, Ove (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Kommunikationsteknologi,Forskargrupper vid Lunds universitet,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Communications Engineering,Lund University Research Groups
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- Öwall, Viktor (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Integrated Electronic Systems,Lund University Research Groups
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- Liu, Liang (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Integrated Electronic Systems,Lund University Research Groups
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(creator_code:org_t)
- 2017
- 2017
- Engelska 4 s.
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings. - 9781509014279 - 9781467368537 ; , s. 1-4
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Kommunikationssystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Communication Systems (hsv//eng)
Nyckelord
- FFT
- Massive MIMO
- VLSI implementation
- ASIC implementation
- FPGA implementation
- low latency
- IFFT
Publikations- och innehållstyp
- kon (ämneskategori)
- ref (ämneskategori)
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