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Glitch-Conscious Lo...
Glitch-Conscious Low-Power Design of Arithmetic Circuits
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- Eriksson, Henrik, 1974 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Larsson-Edefors, Per, 1967 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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(creator_code:org_t)
- 2004
- 2004
- English.
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In: 2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004. - 0271-4310. ; 2, s. II281-II284
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Abstract
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- Glitches are common in arithmetic circuits, especially in large multipliers where they often represent the major part of transitions. With the aim to provide a judicious glitch-reduction strategy, we extract and study the relation between generated and propagated glitches for three different arithmetic blocks. We show that the number of propagated glitches is far bigger than those generated regardless of circuit type, supply voltage, and threshold voltage. In contrast to existing glitch-reduction strategies we propose to focus also on the glitch propagation mechanism. It is shown how the inverting property of adder cells can be harnessed to reduce propagation of glitches and thus the overall power dissipation.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences (hsv//eng)
Publication and Content Type
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