Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages

• Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Back-end-of-line (BEOL)

capacitance modeling

Dielectrics

front-end-of-line (FEOL)

III-V.

InGaAs

lateral

LNA

Logic gates

MOSFET

nanowire (NW)

NW circuits

Parasitic capacitance

Photomicrography

Radio frequency

Semiconductor device modeling

Publikations- och innehållstyp

art (ämneskategori)

ref (ämneskategori)