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56 Gbit/s analogue ...
56 Gbit/s analogue PLL for clock recovery
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Schwarz, V. (författare)
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- Willen, Bo G. (författare)
- KTH,Mikroelektronik och informationsteknik, IMIT
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Jackel, H. (författare)
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(creator_code:org_t)
- Institution of Engineering and Technology (IET), 2001
- 2001
- Engelska.
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 37:22, s. 1336-1338
- Relaterad länk:
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https://urn.kb.se/re...
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visa fler...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- A clock-recovery circuit is reported that employs a phase-locked. loop (PLL) at 56.88 Gbit/s. and is demonstrate by locking to a 28.44 GHz sinosoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences, To the knowledge of the authors, this is the First demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s.
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- art (ämneskategori)
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