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A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
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- Vangal, Sriram (author)
- Linköpings universitet,Institutionen för systemteknik,Tekniska högskolan
- Singh, A. (author)
- Howard, Jason (author)
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- Dighe, Saurabh (author)
- Borkar, Nitkin (author)
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- (creator_code:org_t)
- IEEE, 2007
- 2007
- English.
- In: 2007 IEEE Symposium on VLSI Circuits. - : IEEE. - 9784900784048 - 9784900784055 ; , s. 42-43
- Conference paper (peer-reviewed)
Abstract
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- A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.
Keyword
- TECHNOLOGY
- TEKNIKVETENSKAP
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- ref (subject category)
- kon (subject category)
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