Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm

Qureshi, Fahad (author): Linköpings universitet,Elektroniksystem,Tekniska högskolan

Garrido, Mario (author): Linköpings universitet,Elektroniksystem,Tekniska högskolan

Gustafsson, Oscar (author): Linköpings universitet,Elektroniksystem,Tekniska högskolan

(creator_code:org_t)

2013-02
2013
English.
In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 49:5, s. 348-U60

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Abstract Subject headings

A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7-point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.

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