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SAT-based Counterexample-Guided Inductive Synthesis of Distributed Controllers

Chukharev, Konstantin (author)
Sirius University of Science and Technology, 1 Olympic Ave, 354340, Sochi, Russia. Computer Technologies Laboratory, ITMO University, St. Petersburg, Russia
Suvorov, Dmitrii (author)
Sirius University of Science and Technology, 1 Olympic Ave, 354340, Sochi, Russia. Computer Technologies Laboratory, ITMO University, St. Petersburg, Russia
Chivilikhin, Daniil (author)
Sirius University of Science and Technology, 1 Olympic Ave, 354340, Sochi, Russia. Computer Technologies Laboratory, ITMO University, St. Petersburg, Russia
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Vyatkin, Valeriy (author)
Luleå tekniska universitet,Datavetenskap,Computer Technologies Laboratory, ITMO University, St. Petersburg, Russia. Department of Electrical Engineering and Automation, Aalto University, Espoo, Finland
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Sirius University of Science and Technology, 1 Olympic Ave, 354340, Sochi, Russia Computer Technologies Laboratory, ITMO University, St. Petersburg, Russia Datavetenskap (creator_code:org_t)
IEEE, 2020
2020
English.
In: IEEE Access. - : IEEE. - 2169-3536. ; 8, s. 207485-207498
  • Journal article (peer-reviewed)
Abstract Subject headings
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  • This paper proposes a new method for automatic synthesis of distributed discrete-state controllers from given temporal specification and behavior examples. The proposed method develops known synthesis methods to the distributed case, which is a fundamental extension. This method can be applied for automatic generation of correct-by-design distributed control software for industrial automation. The proposed approach is based on reduction to the Boolean satisfiability problem (SAT) and has Counterexample-Guided Inductive Synthesis (CEGIS) at its core. We evaluate the proposed approach using the classical distributed alternating bit protocol.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)

Keyword

Control system synthesis
Inference algorithms
Boolean satisfiability
Counterexample-guided inductive synthesis
Formal verification
Model checking
Dependable Communication and Computation Systems
Kommunikations- och beräkningssystem

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