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Energy-Efficient Application-Specific Instruction-Set Processor for Feature Extraction in Smart Vision Systems
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- Ferreira, Lucas (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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- Malkowsky, Steffen (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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- Persson, Patrik (author)
- Lund University,Lunds universitet,Matematik LTH,Matematikcentrum,Institutioner vid LTH,Lunds Tekniska Högskola,Mathematics (Faculty of Engineering),Centre for Mathematical Sciences,Departments at LTH,Faculty of Engineering, LTH
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- Matthews, Michael B. (editor)
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- (creator_code:org_t)
- 2021
- 2021
- English 5 s.
- In: Conference Record - Asilomar Conference on Signals, Systems and Computers. - 1058-6393. - 9781665458283 ; 2021-October, s. 324-328
- Conference paper (peer-reviewed)
Abstract
Subject headings
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- Smart vision sensor systems enable many computer vision applications such as autonomous drones and wearable devices. These battery-powered gadgets have very stringent power consumption requirements. Close-to-sensor feature extraction compressing the full image into descriptive keypoints, is crucial as it allows for several design optimizations. First, the amount of necessary on-chip memory can be lessened. Second, the volume of data that needs to be exchanged between nodes in Internet of Things (IoT) applications can also be reduced. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) tailored to perform energy-efficient feature extraction in real-time. The ASIP features a Very Long Instruction Word (VLIW) central core comprising one RV32I RISCV and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. As a case study, Oriented FAST and Rotated BRIEF (ORB) is used to evaluate the proposed architecture. We show that the architecture supports VGA-resolution images at 140 Frames-Per-Second (FPS), for one scale, reducing the number of memory accesses by 2 orders of magnitude comparing to other embedded general-purpose architectures.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Keyword
- ASIP
- Feature Extraction
- ORB
- vision-based Simultaneous Localization And Mapping (SLAM)
Publication and Content Type
- kon (subject category)
- ref (subject category)
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