An Application Specific Vector Processor for Efficient Massive MIMO Processing

• This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm $^2$ for a $128\times 8$ massive MIMO system.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Engineering (hsv//eng)

Keyword

5G

accelerator architecture

ASIP

Baseband

baseband processor

communications processor

Complexity theory

Computer architecture

computer architecture

Massive MIMO

massive MIMO

Mathematical models

Matrix decomposition

matrix processor

parallel memory

Precoding

programmable processor

SIMD

systolic arrays

vector processor

VLIW

Publication and Content Type

art (subject category)

ref (subject category)