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gm/Id Analysis of vertical nanowire III–V TFETs
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- Rangasamy, Gautham (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Nanoelektronik,Forskargrupper vid Lunds universitet,LTH profilområde: AI och digitalisering,LTH profilområden,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Nano Electronics,Lund University Research Groups,LTH Profile Area: AI and Digitalization,LTH Profile areas,Faculty of Engineering, LTH
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- Zhu, Zhongyunshen (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Nanoelektronik,Forskargrupper vid Lunds universitet,LTH profilområde: AI och digitalisering,LTH profilområden,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Nano Electronics,Lund University Research Groups,LTH Profile Area: AI and Digitalization,LTH Profile areas,Faculty of Engineering, LTH
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- Ohlsson Fhager, Lars (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Nanoelektronik,Forskargrupper vid Lunds universitet,LTH profilområde: Nanovetenskap och halvledarteknologi,LTH profilområden,LTH profilområde: AI och digitalisering,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Nano Electronics,Lund University Research Groups,LTH Profile Area: Nanoscience and Semiconductor Technology,LTH Profile areas,Faculty of Engineering, LTH,LTH Profile Area: AI and Digitalization,Faculty of Engineering, LTH
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- 2023
- 2023
- English.
- In: Electronics Letters. - 1350-911X. ; 59:18
- Journal article (peer-reviewed)
Abstract
Subject headings
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- Experimental data on analog performance of gate-all-around III-V vertical Tunnel Field-Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current-mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
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