Design space exploration for field programmable compressor trees

Cevrero, Alessandro (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

Brisk, Philip (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

Nicopoulos, Chrysostomos (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

Gurkaynak, Frank K. (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

Leblebici, Yusuf (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

Ienne, Paolo (author): Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland

(creator_code:org_t)

2008-10-19
2008
English.
In: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems. - New York : ACM Press. ; , s. 207-216

Related links:: https://kth.diva-por... (primary) (Raw object); show more...; http://kth.diva-port...; https://urn.kb.se/re...; https://doi.org/10.1...; show less...

Abstract Subject headings

The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor’s largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.

By the author/editor: Attarzadeh Niaki ...; Cevrero, Alessan ...; Brisk, Philip; Nicopoulos, Chry ...; Gurkaynak, Frank ...; Leblebici, Yusuf; show more...; Ienne, Paolo; show less...

About the subject

ENGINEERING AND TECHNOLOGY: ENGINEERING AND ...; and Electrical Engin ...; and Embedded Systems

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