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TFET inverter static and transient performances in presence of traps and localized strain
- Gnani, E. (author)
-
- Visciarelli, Michele (author)
- KTH,Skolan för teknikvetenskap (SCI)
- Gnudi, A. (author)
- show more...
- Reggiani, S. (author)
- Baccarani, G. (author)
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- (creator_code:org_t)
- PERGAMON-ELSEVIER SCIENCE LTD, 2019
- 2019
- English.
- In: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 159, s. 38-42
- Journal article (peer-reviewed)
Abstract
Subject headings
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- This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I-OFF values, namely 100 nA/mu m and 10 pA/mu m to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I-OFF = 10 pA/mu m.
Keyword
- Tunnel field-effect transistors (TFET)
- III-V materials
- Strain
- Interface traps
- Quantum transport
- TFET inverter
Publication and Content Type
- ref (subject category)
- art (subject category)
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