WFRF:(Caputa Peter)
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| Fältnamn | Indikatorer | Metadata |
|---|---|---|
| 000 | 02301naa a2200469 4500 | |
| 001 | oai:DiVA.org:liu-13914 | |
| 003 | SwePub | |
| 008 | 060718s2006 | |||||||||||000 ||eng| | |
| 024 | 7 | a https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-139142 URI |
| 024 | 7 | a https://doi.org/10.1109/ISSCC.2006.16962332 DOI |
| 040 | a (SwePub)liu | |
| 041 | a engb eng | |
| 042 | 9 SwePub | |
| 072 | 7 | a vet2 swepub-contenttype |
| 072 | 7 | a kon2 swepub-publicationtype |
| 100 | 1 | a Caputa, Peteru Linköpings universitet,Elektroniska komponenter,Tekniska högskolan4 aut0 (Swepub:liu)petca37 |
| 245 | 1 0 | a An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme |
| 264 | 1 | c 2006 |
| 338 | a print2 rdacarrier | |
| 520 | a A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs. | |
| 653 | a CMOS integrated circuits | |
| 653 | a delays | |
| 653 | a integrated circuit design | |
| 653 | a integrated circuit interconnections | |
| 653 | a synchronisation | |
| 653 | a 0.18 micron | |
| 653 | a 5.4 mm | |
| 653 | a CMOS process | |
| 653 | a data synchronization | |
| 653 | a data-clock skew | |
| 653 | a global clock skew | |
| 653 | a multicycle communication | |
| 653 | a on-chip global wire delays | |
| 653 | a synchronous latency-insensitive design | |
| 653 | a TECHNOLOGY | |
| 653 | a TEKNIKVETENSKAP | |
| 700 | 1 | a Svensson, Christeru Linköpings universitet,Elektroniska komponenter,Tekniska högskolan4 aut0 (Swepub:liu)chrsv76 |
| 710 | 2 | a Linköpings universitetb Elektroniska komponenter4 org |
| 773 | 0 | t International Solid-State Circuits Conference 2006, San Fransisco, USAz 1424400791 |
| 856 | 4 | u http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7123y Link to Ph.D. thesis |
| 856 | 4 8 | u https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-13914 |
| 856 | 4 8 | u https://doi.org/10.1109/ISSCC.2006.1696233 |
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