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> (2010-2014) >
Handling Shared Var...
Abstract
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- Parallelized shared variable applications running on multi-core Network-on-Chips(NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, we propose a dedicated hardware module forsynchronization management. This module is called Synchronization Handler (SH), integrated with each processor-memory node on the multi-core NoCs. It uses two physical buffers to concurrently process synchronization requests issued by the local processor and remote processors via the on-chip network. One salient feature is that the two physical buffers are dynamically allocated to form multiple virtual buffers (a virtual buffer is related to a shared synchronization variable) so as to improve the buffer utilization and alleviate the head-of-line blocking. Synthesis results suggest that the SH can run over 900 MHz in 130nm technology with small area overhead. To justify the SH-enhanced multicore NoCs, we employ synthetic workloads to evaluate synchronizationcost and buffer utilization, and run synchronization-intensive applications to investigate speedup. The results show that our approach is viable.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- 900 MHz
- Buffer utilization
- Critical Paths
- Dedicated hardware
- Distributed Memory
- Head of line blocking
- Multi core
- Network-on-chips
- On-chip networks
- Performance penalties
- Process synchronization
- Processor-memory
- Remote processors
- Salient features
- Shared variables
- Small area
- Synchronization cost
- Synthetic workloads
Publication and Content Type
- ref (subject category)
- kon (subject category)
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