High-k/InGaAs interface defects at cryogenic temperature

• Oxide defects in the high-k/InGaAs MOS system are investigated. The behaviour of these traps is explored from room temperature down to 10 K. This study reveals that the exchange of free carriers between oxide states and either the conduction or the valence band is strongly temperature dependant. The capture and emission of electrons is strongly suppressed at 10 K as demonstrated by the collapse of the capacitance frequency dispersion in accumulation for n-InGaAs MOS devices, though hysteresis in the C-V sweeps is still present at 10 K. Phonon assisted tunnelling processes are considered in the simulation of electrical characteristics. The simulated data match very well the experimental characteristics and provide energy and spatial mapping of oxide defects. The multi phonon theory also help explain the impedance data temperature dependence. This study also reveals an asymmetry in the free carrier trapping between n and p type devices, where hole trapping is more significant at 10 K.

Subject headings

NATURVETENSKAP  -- Fysik -- Den kondenserade materiens fysik (hsv//swe)

NATURAL SCIENCES  -- Physical Sciences -- Condensed Matter Physics (hsv//eng)

Keyword

Cryogenic impedance measurements

Device simulation

High-k/InGaAs interface defects

Oxide defects

Publication and Content Type

art (subject category)

ref (subject category)