A deadlock-free fault-tolerant routing algorithm based on pseudo-receiving mechanism for networks-on-chip of CMP

QC 20140909
As the size of CMOS technology scales down to nanometers domain, fault-tolerant is becoming a challenge for NoC. Turn model provides a simple and efficient systematic approach to the development of deadlock-free routing algorithms. In this paper, we propose a pseudo-receiving mechanism based on the support of local processor's cache to enable prohibited turn, and meanwhile make it keep deadlockfree. We present a fault-tolerant routing algorithm based on pseudo-receiving mechanism for 2D mesh. The routing algorithm is livelock-free in the cost of disable a few un-faulty links or nodes. The algorithm is applied to a single-cycle fixed output-buffered router. Experimental results show that, it achieves high performance even under high faulty rate.

NATURVETENSKAP Data- och informationsvetenskap Systemvetenskap, informationssystem och informatik hsv//swe
NATURAL SCIENCES Computer and Information Sciences Information Systems hsv//eng
Chip multiprocessor
Fault-tolerant routing
Networks-on-chip
Turn model
CMOS technology
Deadlock-free routing
Fault tolerant routing
Fault-tolerant
Fault-tolerant routing algorithm
Networks on chips
Single cycle
Algorithms
CMOS integrated circuits
Microprocessor chips
Routers
Routing algorithms
Network architecture

Ingår i:2011 International Conference on Multimedia Technology, ICMT 2011, s. 2825-28289781612847719

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NATURVETENSKAP: NATURVETENSKAP; och Data och informa ...; och Systemvetenskap ...

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